This application claims the priority benefit of Taiwan application serial no. 90108178, filed on Apr. 4, 2001.
1. Field of the Invention
The invention relates in general to a design of configuration space. More particularly, the invention relates to a method of dividing a configuration space.
2. Description of the Related Art
A north bridge control chip and a south bridge control chip normally exist in a conventional computer system using the PCI bus. FIG. 1 shows a conventional PCI bus system structure and the distributed locations of the configuration spaces thereof. In FIG. 1, in a PCI bus system, a north bridge control chip 100 comprises a configuration space for host bridge 160. The configuration values of the microprocessor 110, the memory system 150 and the PCI bus 120 are stored in the registers of the configuration space for host bridge 160. Similarly, the south bridge control chip 130 comprises a configuration space for the ISA bridge 190 to store the configuration values required by the peripherals connected to the south bridge control chip. In FIG. 1, the north bridge control chip 100 is responsible for connecting the microprocessor 110 and a 33 MHz PCI bus 120, while the south bridge control chip 130 is responsible for connecting the peripherals such as the USB controller and the IDE controller to the 33 MHz PCI bus 120. A LAN controller may also use the 33 MHz PCI bus to connect a memory system such as a DRAM. As the transmission speed of the memory bus and the peripherals is increased, a bottleneck of data transmission speed falls on the PCI bus with only a speed of 33 MHz.
The invention provides a method of distribution and storage of a configuration space that can be applied to an advanced computer system without modifying the BIOS or system software used in the conventional computer system. That is, for the BIOS or OS system development, the advanced computer system does not have any change in the access method and structure of configuration.
A method of dividing a configuration space is provided by the invention. The method can be applied to a computer system using a PCI bus, especially to an advanced computer system that quotes a high speed private bus between a north bridge control chip and a south bridge control chip. The computer system comprises a microprocessor, a host bus, the north bridge control chip, the high speed private bus, a PCI bus, the south bridge control chip, a memory bus, and a memory system. The host bus connects the microprocessor to the north bridge control chip. The high speed private bus is responsible for connecting the north bridge control chip to the south bridge control chip. Using the south bridge control chip, the PCI bus is connected to the host bus or the memory bus via the high speed private bus. The method provides an actual configuration space A stored in the north bridge control chip to store the configuration value relating to the microprocessor and the memory system. The method also provides an actual configuration storage space B in the south bridge control chip to store the configuration value relating to the PCI bus. In addition, the method provides a duplicated copy of configuration storage space B(A) in the north bridge control chip (south bridge control chip). Such duplicated copy of configuration storage space is an empty configuration space. The method further provides a selector in the north bridge control chip to select data to be read according to the specific requirement.
When the microprocessor intends to perform an operation of writing a configuration value, and if the data is to be written into the actual storage configuration space A of the north bridge control chip, the north bridge control chip executes the write operation. Meanwhile, the north bridge control chip also informs the south bridge control chip that the data is written into the duplicated copy of configuration space A of the south bridge control chip. If the data is written into the actual configuration storage space B of the south bridge control chip, in addition to send the write request to the south bridge control chip, the north bridge control chip also executes a write operation on the duplicated copy of configuration space B of the north bridge control chip. If the microprocessor is to perform a read operation on the configuration data, the read request is sent to both the north and south bridge control chips. Meanwhile, according to the read address, the selector located in the north bridge control chip determines such data is obtained from either the actual configuration space A of the north bridge control chip, or the actual configuration space B of the south bridge control chip.
Thus, to the microprocessor, it seems that all the configuration data are stored in the north bridge control chip. But actually, some configuration values related to the PCI bus are stored in the south bridge control chip. The design can conceal the influence caused by the quotation of a high speed private bus in the advanced computer system, but meet the requirement of dividing the configuration space distribution in the advanced system.
For the BIOS or OS system, the configuration space is equivalently undivided such that the original software program does not have to be modified correspondingly. But in fact, the configuration space is stored in the north bridge control chip and the south bridge control chip according to the specific requirement, respectively. The advanced computer system can thus quote a high speed private bus between the north and south bridge control chips to enhance the transmission functions.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.